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document order number: mpc17c724 rev 2.0, 12/2005 freescale semiconductor technical data * this document contains certain information on a new product. specifications and information herein are subject to change without notice. ? freescale semiconductor, in c., 2005. all rights reserved. 0.4 a dual h-bridge motor driver ic the 17c724 is a compact monolithic dual channel h-bridge power ic, ideal for portable electronic applications containing bipolar stepper motors or brush dc motors such as those used in camera lenses and shutters. the 17c724 can operate efficiently with supply voltages from 2.7 v to 5.5 v and can provide continuous motor drive currents of 0.4 a with low rds(on) of 1.0 ? . it is easily interfaced to low-cost mcus via parallel 3.0 v- or 5.0 v-compatible logic and has built-in shoot- through current protection circuit and undervoltage detector to avoid malfunction. the 17c724 has four output contro l modes: forward, reverse, brake, and tri-state (high impedanc e). the h-bridge outputs are designed to be independently pwm?ed at up to 200 khz for speed/ torque and current control. features ? manufactured in smos7 process technology ? built-in 2-channel h-bridge driver ? provides 4 driving modes (forward, reverse, break, high impedance) ? direct interface to mcu ? low on-resistance, r ds(on) = 1.0 ? (typical) ? dual channel parallel drive, r ds(on) = 0.5 ? (typical) ? output current driver (idr) is 400 ma (continuous) ? low power consumption ? built-in shoot-through current prevention circuit ? built-in low-voltage shutdown circuit ? pwm control frequency 200 khz (max) ? very compact size, comes in 16-terminal qf n package (3 x 3 mm terminal pitch: 0.5 mm) ? pb-free packaging designated by suffix code ep figure 1. 17c724 simplified application diagram scale 4:1 motor driver ep (pb-free) suffix 98arl10566d 16-terminal qfn 17c724 ordering information device temperature range (t a ) package MPC17C724EP/r2 -20c to 85c 16 qfn mcu 3.0 v 17c724 bipola r step motor vdd vm out1a out1b out2b out2a gnd in1a in1b in2a in2b psave n s
analog integrated circuit device data 2 freescale semiconductor 17c724 internal block diagram internal block diagram figure 2. 17c724 simplified internal block diagram pgnd2 pgnd2 out2b out2a vm2 pgnd1 out1a out1b vm1 level shifter predriver control logic vdd low- voltage shutdown psave- in1a in1b psave in2a in2b lgnd vdd h-bridge 2 h-bridge 1
analog integrated circuit device data freescale semiconductor 3 17c724 terminal connections terminal connections figure 3. 17c724 terminal connections table 1. 17c724 terminal definitions a functional description of each terminal can be found in the functional terminal description section beginning on page 8 . terminal number terminal name terminal function formal name definition 1 in1a logic logic input control 1a logic input control of out1a (refer to table 5, truth table , page 7 ). 2 in1b logic logic input control 1b logic input control of out1b (refer to table 5, truth table , page 7 ). 3 out1a output h-bridge output 1a output a of h-bridge channel 1. 4 vm1 power motor driver power supply 1 positive power source connection fo r h-bridge 1 (motor driver power supply) (1) . 5 out2a output h-bridge output 2a output a of h-bridge channel 2. 6, 7 pgnd2 ground power ground 2 high-current power ground 2 (2) . 8 out2b output h-bridge output 2b output b of h-bridge channel 2. 9 vm2 power motor driver power supply 2 positive power source connection fo r h-bridge 2 (motor driver power supply) (1) . 10 out1b output h-bridge output 1b output b of h-bridge channel 1. 11 in2b input logic input control 2b logic input control of out2b (refer to table 5, truth table , page 7 ). 12 in2a input logic input control 2a logic input control of out2a (refer to table 5, truth table , page 7 ). 13 psave input input enable control logic input enable control of h-bridges to save power. 14 lgnd ground logic ground low-current logic signal ground (2) . 15 pgnd1 ground power ground 1 high-current power ground 1 (2) . 16 vdd logic logic circuit power supply positive power source c onnection for logic circuit. notes 1. vm1 and vm2 are internally connected. 2. lgnd, pgnd1, and pgnd2 are internally connected. transparent top view of package 1n1a out1a vm1 1n1b out2a pgnd2 pgnd2 out2b 15 5 4 3 2 1 in2a out1b vm2 in2b 10 9 14 13 11 12 8 pgnd1 lgnd psave 16 67 vdd
analog integrated circuit device data 4 freescale semiconductor 17c724 maximum ratings maximum ratings table 2. maximum ratings all voltages are with respect to ground unless otherwise no ted. exceeding these ratings may cause a malfunction or permanent damage to the device. ratings symbol value unit electrical ratings power supply voltage (motor driver) normal operation (steady-state) transient conditions (3) v m(ss) v m(pk) - 0.3 to 6.0 - 0.3 to 6.5 v logic supply voltage v dd 6.0 v input terminal voltage v in - 0.3 to v dd + 0.3 v driver output current (continuous) (4) i o 400 ma driver output current (peak) (5) i opk 800 ma esd voltage (6) human body model machine model v esd1 v esd2 2000 200 v temperature ratings storage temperature t stg - 40 to 150 c operating temperature ambient t a - 20 to 85 c operating junction temperature t j 150 maximum c thermal resistance (junction-to-ambient) single-layer pcb mounting (8) multi-layer pcb (2s2p) mounting (9) r ja r jma 169 47 c/w terminal soldering temperature (7) t solder 260 c notes 3. transient condition within 500 ms. 4. continuous output current must not be exceeded and at operating junction temperature below 150 c. 5. peak time is for 10 ms pul se width at 200 ms intervals. 6. esd testing is performed in accordance with the human body model (c zap = 100 pf, r zap = 1500 ?), and the machine model (c zap = 200 pf, r zap = 0 ? ). 7. terminal soldering temperature limit is for 10 seconds maximu m duration. not designed for imme rsion soldering. exceeding thes e limits may cause malfunction or permanent damage to the device. 8. for cases using semi g38-87, jedec jesd51-2, jesd51-3, jesd51-5, single layer pcb mounting without thermal vias. 9. for cases using semi jedec jesd51-6, jesd51-5, jesd51-7, 2s2p pcb mounting with 4 thermal vias.
analog integrated circuit device data freescale semiconductor 5 17c724 static electrical characteristics static electrical characteristics table 3. static electric al characteristics characteristics noted under conditions ta = 25c, v dd = vm = 3 . 0v, unless otherwise noted. typical values noted reflect the approximate parameter means at t a = 25c under nominal conditions unless otherwise noted. characteristic symbol min typ max unit power input (vdd, psave) supply voltage range motor driver supply voltage logic supply voltage v m v dd 2.7 2.7 3.0 3.0 5.5 5.5 v standby power supply current (10) v m = 3.0 v v dd = 3.0 v i v mstby i v ddstby ? ? ? ? 1.0 1.0 a operating power supply current (11) v dd = 3.0 v i c ? 40 100 a logic input function high-level input voltage low-level input voltage high-level input current low-level input current psave terminal low level input current (12) v ih v il i. ih i il i il v dd 0.7 ? ? - 1.0 ? ? ? ? ? - 30 ? v dd 0.3 1.0 ? - 60 v v a a a driver output on resistance (13) r ds(on) ? 1.0 1.5 ? low-voltage shutdown detection voltage (14) v dd det 1.5 2.0 2.5 v notes 10. power save mode. 11. i c is the sum of the current of v dd monitor block ?low voltage detection module? and the psave pull-up resistor at f in = 200 khz. 12. v dd = 3.0 v. 13. i o = 375 ma. r ds(on) = r source + r sink . r l = 6.8 ? . 14. detection voltage is defined as when the output becomes high impedance after v dd voltage falls and when v m = 5.5 v.
analog integrated circuit device data 6 freescale semiconductor 17c724 dynamic electrical characteristics dynamic electrical characteristics table 4. dynamic electri cal characteristics characteristics noted under conditions ta = 25c, v dd = vm = 3.0v, unless otherwise noted. typical values noted reflect the approximate parameter means at t a = 25c under nominal conditions unless otherwise noted. characteristic symbol min typ max unit input pulse input frequency f in ? ? 200 khz input pulse rise time (15) t r ? ? 1.0 (16) s input pulse fall time (17) t f ? ? 1.0 (16) s output output propagation delay time (18) turn-on time turn-off time t plh t phl ? ? 0.2 0.1 0.5 0.5 s low-voltage detection time t v dd det ? 0.02 1.0 ms notes 15. time is defined between 10% and 90%. 16. that is, the input waveform slope must be steeper than this. 17. time is defined between 90% and 10%. 18. r l = 6.8 ? . slew time, rise time, and fall times are between 10% and 90% of output low and high levels with respect to the 50% level of the input.
analog integrated circuit device data freescale semiconductor 7 17c724 timing diagrams timing diagrams figure 4. t plh and t phl timing figure 5. low-voltage detection timing table 5. truth table 10% 50% outa, outb 90% t plh t phl in1, in2, psave t v dd det 0% v dd i m 50% t v dd det 1.0 v 2.5 v v dd deton v dd detoff 90% (<1.0 a) input output v dd det (20) psave (19) in1a in2a in1b in2b out1a out2a out1b out2b llllle nabled l h l h l enabled l l h l h enabled l h h z z enabled hxxzzdisabled h : high l : low z : high impedance x : don?t care notes 19. terminal 13 (psave) is pulled up by an internal resistor. 20. when v dd is lower than v dd det while v m is applied, output becomes ?z? (high impedance); however, when psave = ?h?, the low-voltage shutdown detec tion circuit is disabled.
analog integrated circuit device data 8 freescale semiconductor 17c724 functional description introduction functional description introduction the 17c724 is a monolithic dual h-bridge that is ideal in portable electronic applications to control bipolar step motors and brush dc motors such as those used in camera lens and shutters. the 17c724 can oper ate efficiently with supply voltages as low as 2.7 v to as high as 5.5 v, and provide continuous motor drive currents of 0.4 a while handling peak currents up to 0.8 a. it is easily interfaced to low-cost mcus via parallel 3.0 v- or 5.0 v-compatible logic. the device can be pulse width modulated (pwm?ed) at up to 200 khz. the 17c724 can drive two motors simultaneously (see figure 6 ), or it can drive one bipolar step motor as shown in the simplified application diagram on page 1 . dual channel parallel drive is also possible if higher current drive is desired (0.8 a). two-motor operation is accomplished by hooking one motor between out1a and out1b, and the other motor between out2a and out2b. this ic has a built-in shoo t-through current protection circuit and undervoltage detector to avoid malfunction. it also allows for power-conserving sleep mode by the setting of the psave terminal (refer to table 5, truth table , page 7 ). the device features four operating modes: forward, reverse, brake, and tri-stated (high impedance). functional terminal description logic circuit power supply (vdd) the vdd terminal carries the power source connection to the control (logic) circuit, and its input range is between 2.7 v to 5.5 v (3.0 v and 5.0 v compatible). v dd has an undervoltage threshold. if the supply voltage to v dd drops below 2.0 v (typical), then al l the output of h-bridges (out1a, out1b, out2a, out2b) will become open (high impedance = z). when the supply voltage returns to a level that is above the threshold voltage the h-bridge outputs automatically resume normal operation according to the established condition of the input terminals. logic input control (in1a, in1b, in2a, and in2b) these logic input terminals control each h-bridge output. for example, in1a logic hi gh = out1a high; likewise, in1b logic high = out1b high. if both a and b inputs are high, then both a and b outputs are z (refer to table 5, truth table , page 7 ). input enable control (psave) the psave input controls the functioning of the power output stages (the h-brid ges). when it is set logic low, the output stages are enabled and the h-bridges function normally. when it is set logic high, the output stages are disabled and all the outputs are opened (high impedance). in this mode, the built-in low-voltage detection circuit is disabled. h-bridge output (out1a , out1b, out2a, and out2b) these terminals are the outputs of the power mosfet h-bridges. out1 is from h-bridge channel 1, and out2 from h-bridge channel 2. these terminals will typically connect to an external load (step motor or brush dc motors). motor driver power supply (vm1 and vm2) vm1 and vm2 carries the main supply voltage and current into the power sections (the h-bridges) of the ic. both of these terminals are connected internally but they must be connected together on the printe d circuit board with as short as possible traces. the input range is 2.7 v to 5.5 v. power ground (pgnd1 and pgnd2) these two are the power ground terminals that connect to the power ground of the h-bri dges. the power grounds are for higher current handling capability from loads and they must be connected together on the pcb. logic ground (lgnd) lgnd is the logic ground terminal and its current handling level is lower than the pgnd.
analog integrated circuit device data freescale semiconductor 9 17c724 typical applications functional terminal description typical applications figure 6 shows a typical application for the 17c724. figure 6. 17c724 typical application diagram cemf snubbing techniques care must be taken to protect the ic from potentially damaging cemf spikes induced when commutating currents in inductive loads. typical practice is to provide snubbing of voltage transients by placing a zener or capacitor at the supply terminal (vm) (see figure 7 ). figure 7. cemf snubbing techniques pcb layout when designing the printed circuit board (pcb), connect sufficient capacitance between power supply and ground terminals to ensure proper filter ing from transients. for all high-current paths, use wide co pper traces and shortest possible distance. application notes although vm1 and vm2 are connected internally, they must be connected externally to attain sufficient power distribution. take precautions to guard against electrostatic discharge when handling the device, especially when mounting and demounting the device to a pcb. mcu 17c724 3.0 v gnd in1b in2a in2b psave vm out1b out2b out1a in1a out2a vdd 17c724 3.0 v 3.0 v gnd vm v dd out out out out 17c724 3.0 v 3.0 v gnd vm v dd out out out out
analog integrated circuit device data 10 freescale semiconductor 17c724 packaging package dimensions packaging package dimensions for the most current package revision, visit www.freescale.com and perform a keyword search using the ?98a? listed below. ep (pb-free) suffix 16-terminal qfn non-leaded package 98arl10566d issue a
analog integrated circuit device data freescale semiconductor 11 17c724 packaging package dimensions ep (pb-free) suffix 16-terminal qfn non-leaded package 98arl10566d issue a
analog integrated circuit device data 12 freescale semiconductor 17c724 revision history revision history revision date description of changes 2.0 2005 ? initial release
mpc17c724 rev 2.0 12/2005 information in this document is provided solely to enable system and software implementers to use freescale semiconduc tor products. there are no express or implied copyright licenses granted hereunder to design or fabricate any integrated circuits or integrated circuits based on the information in this document. freescale semiconductor reserves the right to make changes without further notice to any products herein. freescale semiconductor makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does freescale semiconductor assume any liability ar ising out of the application or use of any product or circuit, and specifically discl aims any and all liability, including without limitation consequential or incidental damages. ?typical? parameters that may be provided in freescale semiconductor data s heets and/or specifications can and do vary in different applications and actual performance may vary over time. all operating parameters, including ?typicals?, must be validated for each customer application by customer?s technical experts. freescale se miconductor does not convey any license under its patent rights nor the rights of others. freescale semiconductor products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the fa ilure of the freescale semiconductor product could create a situation where personal injury or death may occur. should buyer purchase or use freescale semiconductor products for any such unintended or unauthorized application, buyer shall indemni fy and hold freescale semiconductor and its officers, employees, subsidiaries, affili ates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that freescale semiconductor was negligent regarding the design or manufacture of the part. freescale? and the freescale logo are trademarks of freescale semiconductor, inc. all other product or service names are the property of their respective owners. ? freescale semiconductor, inc., 2005. all rights reserved. how to reach us: home page: www.freescale.com e-mail: support@freescale.com usa/europe or locations not listed: freescale semiconductor technical information center, ch370 1300 n. alma school road chandler, arizona 85224 +1-800-521-6274 or +1-480-768-2130 support@freescale.com europe, middle east, and africa: freescale halbleiter deutschland gmbh technical information center schatzbogen 7 81829 muenchen, germany +44 1296 380 456 (english) +46 8 52200080 (english) +49 89 92103 559 (german) +33 1 69 35 48 48 (french) support@freescale.com japan: freescale semiconductor japan ltd. headquarters arco tower 15f 1-8-1, shimo-meguro, meguro-ku, tokyo 153-0064 japan 0120 191014 or +81 3 5437 9125 support.japan@freescale.com asia/pacific: freescale semiconductor hong kong ltd. technical information center 2 dai king street tai po industrial estate tai po, n.t., hong kong +800 2666 8080 support.asia@freescale.com for literature requests only: freescale semiconductor literature distribution center p.o. box 5405 denver, colorado 80217 1-800-441-2447 or 303-675-2140 fax: 303-675-2150 ldcforfreescalesemiconductor@hibbertgroup.com rohs-compliant and/or pb-free versions of freescale products have the functionality and electrical characteristics of thei r non-rohs-compliant and/or non-pb-free counterparts. for further information, see http://www.freescale.com or contact your freescale sales representative. for information on freescale?s environmental products program, go to http:// www.freescale.com/epp .

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